Friday, December 17, 2010

Google is the big brand in chip software, says EDA exec


 Dramatically shortened design cycles and the rise of software defined applications have changed the design flow of system-on-chip devices, says EDA tool supplier.
“Today we are seeing one to ten million gate SoCs being designed in three to six month,” said Steve Brown, product management director at Cadence Design Systems,
“This is an incredibly short period of time to achieve this and requires significant changes in the design flow,” said Brown.  
“Ten million gate chips with software that is fully verified in three to six months, this is the big issue the design community is facing,” said Brown.
A major change, says Brown, is the way in which high level software, such as operating system and applications software, is defining the performance and operation of these large ICs.
“The big brand in the market is Google and its Android operation system,” said Brown.

“The challenge for designers now is to optimise the SoC for what Google is doing in the market,” said Brown.   
“Software is defining chip design,” said Brown.
This means a fundamental change in the business strategies of design tool firms like Cadence. “We can no longer be just interested in chip design anymore,” said Brown.  
One important area in is the verification of the SoC’s functionality.
Traditional tools to carry out verification will need to change to meet the requirements of very short design cycles and the way software now defines the IC’s function and performance.
“When the design cycle is just 3-6 months the question is becoming ‘what level of verification is enough?’,” said Brown.
But the big challenge is verifying the functionality of the software as well as the hardware.
“We know this works in the chip design, but what will be needed is verification for the software design,” said Brown.
For Cadence, the way forward is to form closer working relationships with semiconductor IP suppliers and software firms.
It is already working closely with processor company ARM. One aspect of this is the speed up the verification of embedded processor IP.
The other is to get involved in system-level design and verification of higher level software functions such as operating system and applications software.     
This change could present some fundamental design issues for tool suppliers, in particular the growth of open source software formations, such as Eclipse.
“Eclipse is not widely proliferated in EDA tools, so how is this going to work out?” asked Brown.
“What will become the language of design – C, UML, CML,” said Brown.

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